Zilog Z80 CPU

This doc is unfinished yet, use it at your own risk :)

Technical description

Source: Wikipedia.

The programming model and register set are conventional and similar to many other processors, such as the related x86 family. The 8080 compatible registers AF, BC, DE, HL are duplicated as two separate banks in the Z80, where the processor can quickly switch from one bank to the other; a feature useful for speeding up responses to single level, high priority interrupts. The dual-register set makes sense as the Z80 (like most microprocessors at the time) was really intended for embedded use, not for personal computers, or the yet-to-be invented home computers. It also turned out to be quite useful for hard-optimized manual assembly coding.

The Z80 architecture. The 8080 compatible registers:

  • AF - 8-bit accumulator (A) and flag bits (F) carry, zero, minus, parity/overflow, half-carry (used for BCD), and an Add/Subtract flag (usually called N) also for BCD
  • BC - 16-bit data/address register or two 8-bit registers
  • DE - 16-bit data/address register or two 8-bit registers
  • HL - 16-bit accumulator/address register or two 8-bit registers
  • SP - stack pointer, 16 bits
  • PC - program counter, 16 bits


Registers introduced with the Z80:

  • IX - 16-bit index or base register for 8-bit immediate offsets
  • IY - 16-bit index or base register for 8-bit immediate offsets
  • I - interrupt vector base register, 8 bits
  • R - DRAM refresh counter, 8 bits (msb does not count)
  • AF' - alternate (or shadow) accumulator and flags (toggled in and out with EX AF,AF' )
  • BC', DE', and HL' - alternate (or shadow) registers (toggled in and out with EXX)
  • Four bits of interrupt status and interrupt mode status

There is no direct access to the alternate registers, instead two special instructions, EX AF,AF' and EXX, each toggles one of two multiplexer flipflops; this enables fast context switches for interrupt service routines: EX AF, AF' may be used alone (for really simple and fast interrupt routines) or together with EXX to swap the whole AF, BC, DE, HL set; still much faster than pushing the same registers on the stack (slower, lower priority, or multi level interrupts normally use the stack to store registers).

The refresh register, R, increments each time the CPU fetches an opcode (or opcode prefix) and has therefore no simple relationship with program execution. This has sometimes been used to generate pseudorandom numbers in games, and also in software protection schemes.

The interrupt vector register, I, is used for the Z80 specific mode 2 interrupts (selected by the im 2 instruction). It supplies the base address for a 128-entry table of service routine addresses which are selected via a pointer sent to the CPU during an interrupt acknowledge cycle. The pointer identifies a particular peripheral chip and/or peripheral function or event, where the chips are normally connected in a so called daisy-chain for priority resolution. Like the refresh register, this register has also sometimes been used creatively.

Instruction set

The tables below list all the Z80 instructions (including the 'undocumented').
On the Amstrad CPC/Plus, the Z80 is clocked to 4MHz. The instructions timing is given in microseconds since all the instructions are rounded up to the nearest M-Cycle (because of the hardware design and bus sharing with the video devices).

Notes:

  • d is a 8bit signed number (-128 to 127)
  • n is a 8bit number
  • nn is a 16bits number
  • r and s means any of the registers A,B,C,D,E,H,L
  • rr and ss means any of the double registers BC,DE,HL,SP
  • qq means any of the double registers BC,DE,HL,AF
  • x/y time is shown for repeating or conditionnal instructions. x is the time when the instruction repeat itself or if it's condition is true. y otherwise.

Flags notations:

  • • flag is not affected
  • x flag is unknown
  • 0 flag is reset
  • 1 flag is set
  • ★ flag is affected according to the result of the operation

8-bit Load

Mnemonic       Symbolic Operation SZ5H4PNC sizetimeOpcode(s)MEMPTR
LD r,sr←s xx 1 1μs %01 -r- -s-
LD r,nr←n xx 2 2μs %00 -r- 110, n
LD r,(HL)r←(HL) xx 1 2μs %01 -r- 110
LD r,(IX+d)r←(IX+d) xx 3 5μs &DD, %01 -r- 110, d
LD r,(IY+d)r←(IY+d) xx 3 5μs &FD, %01 -r- 110, d
LD (HL),r(HL)←r xx 1 2μs %01 110 -r-
LD (IX+d),r(IX+d)←r xx 3 5μs &DD, %01 110 -r-, d
LD (IY+d),r(IY+d)←r xx 3 5μs &FD, %01 110 -r-, d
LD (HL),n(HL)←n xx 2 3μs &36, n
LD (IX+d),n(IX+d)←n xx 4 5μs &DD, &36, d, n
LD (IY+d),n(IY+d)←n xx 4 5μs &FD, &36, d, n
LD A,(BC)A←(BC) xx 1 2μs &0A
LD A,(DE)A←(DE) xx 1 2μs &1A
LD A,(nn)A←(nn) xx 3 4μs &3A, nn.lo, nn.hi
LD (BC),A(BC)←A xx 1 2μs &02
LD (DE),A(DE)←A xx 1 2μs &12
LD (nn),A(nn)←A xx 3 4μs &32, nn.lo, nn.hi
LD A,IA←I xxi0 2 2μs &ED, &57
LD A,RA←R xxi0 2 2μs &ED, &5F
LD I,AI←A xx 2 2μs &ED, &47
LD R,AR←A xx 2 2μs &ED, &4F

~~

~~

r, sRegister
%000B
%001C
%010D
%011E
%100H
%101L
%111A
  • d is a 8bit signed offset
  • n is a 8bit data
  • nn is a 16bit address.
  • i in the P flag is the current IFF0 status:
    • 0: Interrupts are disabled (DI)
    • 1: Interrupts are enabled (EI)

16-bit Load

Mnemonic       Symbolic Operation SZ5H4PNC sizetimeOpcode(s)MEMPTR
LD dd,nndd←nn xx 3 4μs %00 dd0 001, nn.lo, nn.hi
LD IX,nnIX←nn xx 4 4μs &DD, &21, nn.lo, nn.hi
LD IY,nnIY←nn xx 4 4μs &FD, &21, nn.lo, nn.hi
LD HL,(nn)H←(nn+1)
L←(nn+0)
xx 3 5μs &2A, nn.lo, nn.hi
LD dd,(nn)ddh←(nn+1)
ddl←(nn+0)
xx 4 6μs &ED, &2A, nn.lo, nn.hi
LD IX,(nn)IXh←(nn+1)
IXl←(nn+0)
xx 4 6μs &DD, &2A, nn.lo, nn.hi
LD IY,(nn)IYh←(nn+1)
IYl←(nn+0)
xx 4 6μs &FD, &2A, nn.lo, nn.hi
LD (nn),HL(nn+1)←H
(nn+0)←L
xx 3 5μs &22, nn.lo, nn.hi
LD (nn),dd(nn+1)←ddh
(nn+0)←ddl
xx 4 6μs &ED, %01 dd0 011, nn.lo, nn.hi
LD (nn),IX(nn+1)←IXh
(nn+0)←IXl
xx 4 6μs &DD, &22, nn.lo, nn.hi
LD (nn),IY(nn+1)←IYh
(nn+1)←IYl
xx 4 6μs &FD, &22, nn.lo, nn.hi
ddPair
%00BC
%01DE
%10HL
%11SP
  • nn is a 16bit address.

8bits Arithmetic

Mnemonic       Symbolic Operation SZ5H4PNC sizetimeOpcode(s)MEMPTR
ADD A,rA←A+r xxV0 1 1μs
ADD A,nA←A+n xxV0 2 2μs
ADD a,(HL)A←A+(HL) xxV0 1 2μs
ADD A,(IX+d)A←A+(IX+d) xxV0 3 5μs
ADD A,(IY+d)A←A+(IY+d) xxV0 3 5μs
ADC A,rA←A+r+Carry xxV0 1 1μs
ADC A,nA←A+n+Carry xxV0 2 2μs
ADC a,(HL)A←A+(HL)+Carry xxV0 1 2μs
ADC A,(IX+d)A←A+(IX+d)+Carry xxV0 3 5μs
ADC A,(IY+d)A←A+(IY+d)+Carry xxV0 3 5μs
SUB A,rA←A-r xxV1 1 1μs
SUB A,nA←A-n xxV1 2 2μs
SUB a,(HL)A←A-(HL) xxV1 1 2μs
SUB A,(IX+d)A←A-(IX+d) xxV1 3 5μs
SUB A,(IY+d)A←A-(IY+d) xxV1 3 5μs
SBC A,rA←A-r-Carry xxV1 1 1μs
SBC A,nA←A-n-Carry xxV1 2 2μs
SBC a,(HL)A←A-(HL)-Carry xxV1 1 2μs
SBC A,(IX+d)A←A-(IX+d)-Carry xxV1 3 5μs
SBC A,(IY+d)A←A-(IY+d)-Carry xxV1 3 5μs
INC rr←r+1 xxV0 1 1μs
INC (HL)(HL)←(HL)+1 xxV0 1 3μs
INC (IX+d)(IX+d)←(IX+d)+1 xxV0 3 6μs
INC (IY+d)(IY+d)←(HL+d)+1 xxV0 3 6μs
DEC rr←r+1 xxV0 1 1μs
DEC (HL)(HL)←(HL)+1 xxV0 1 3μs
DEC (IX+d)(IX+d)←(IX+d)+1 xxV0 3 6μs
DEC (IY+d)(IY+d)←(HL+d)+1 xxV0 3 6μs
CP rA-r xxV1 1 1μs
CP nA-n xxV1 2 2μs
CP (HL)A-(HL) xxV1 1 2μs
CP (IX+d)A-(IX+d) xxV1 3 5μs
CP (IY+d)A-(IY+d) xxV1 3 5μs

The V symbol in the P/V flag column indicates that the P/V flag contains the overflow of the result of the operation.
V=1 means overflow.

16bits Arithmetic

Mnemonic       Symbolic Operation SZ5H4PNC sizetimeOpcode(s)MEMPTR
ADD HL,ssHL←HL+ss 0 1 3μs
ADC HL,ssHL←HL+ss+Carry 0 2 4μs
SBC HL,ssHL←HL-ss-Carry 0 2 4μs
ADD IX,BCIX←IX+pp 0 2 4μs
ADD IX,DEIX←IX+pp 0 2 4μs
ADD IX,IXIX←IX+pp 0 2 4μs
ADD IX,SPIX←IX+pp 0 2 4μs
ADD IY,BCIY←IY+qq 0 2 4μs
ADD IY,DEIY←IY+qq 0 2 4μs
ADD IY,IYIY←IY+qq 0 2 4μs
ADD IY,SPIY←IY+qq 0 2 4μs
INC ssss←ss+1 1 2μs
INC IXIX←IX+1 2 3μs
INC IYIX←IX-1 2 3μs
DEC ssss←ss+1 1 2μs
DEC IXIX←IX+1 2 3μs
DEC IYIX←IX-1 2 3μs

8bits Logical

Mnemonic       Symbolic Operation SZ5H4PNC sizetimeOpcode(s)MEMPTR
AND rA←A AND r x1xP00 1 1μs
AND nA←A AND n x1xP00 2 2μs
AND (HL)A←A AND (HL) x1xP00 1 2μs
AND (IX+d)A←A AND (IX+d) x1xP00 3 5μs
AND (IY+d)A←A AND (IY+d) x1xP00 3 5μs
OR rA←A OR r x0xP00 1 1μs
OR nA←A OR n x0xP00 2 2μs
OR (HL)A←A OR (HL) x0xP00 1 2μs
OR (IX+d)A←A OR (IX+d) x0xP00 3 5μs
OR (IY+d)A←A OR (IY+d) x0xP00 3 5μs
XOR rA←A XOR r x0xP00 1 1μs
XOR nA←A XOR n x0xP00 2 2μs
XOR (HL)A←A XOR (HL) x0xP00 1 2μs
XOR (IX+d)A←A XOR (IX+d) x0xP00 3 5μs
XOR (IY+d)A←A XOR (IY+d) x0xP00 3 5μs

P=1 mean parity of the result is even.

CPU Control

Mnemonic       Symbolic Operation SZ5H4PNC sizetime

Stack operations

Mnemonic       Symbolic Operation SZ5H4PNC sizetime
LD SP,HLSP←HL xx 1 2μs
LD SP,IXSP←IX xx 2 3μs
LD SP,IYSP←IY xx 2 3μs
PUSH qqSP←SP-2
(SP+1)←qqh
(SP+0)←qql
xx 1 3μs
PUSH IXSP←SP-2
(SP+1)←IXh
(SP+0)←IXl
xx 2 4μs
PUSH IYSP←SP-2
(SP+1)←IYh
(SP+0)←IYl
xx 2 4μs
POP qqqqh←(SP+1)
qql←(SP+0)
SP←SP+2
xx 1 3μs
POP IXIXh←(SP+1)
IXl←(SP+0)
SP←SP+2
xx 2 4μs
POP IYIYh←(SP+1)
IYl←(SP+0)
SP←SP+2
xx 2 4μs

Exchange

Mnemonic       Symbolic Operation SZ5H4PNC sizetime
EX DE,HLDEHL xx 1 1μs
EX AF,AF'AFAF' xx 1 1μs
EXXHLHL'
DE
DE'
BC
BC'
xx 1 1μs
EX (SP),HLH(SP+1)
L
(SP+0)
xx 1 5μs
EX (SP),IXIXh(SP+1)
IXl
(SP+0)
xx 2 6μs
EX (SP),IYIYh(SP+1)
IYl
(SP+0)
xx 2 7μs

Block transfer

Mnemonic       Symbolic Operation SZ5H4PNC sizetime
LDI(DE)←(HL)
DE←DE+1
HL←HL+1
BC←BC-1
x0x0 2 5μs
LDIR(DE)←(HL)
DE←DE+1
HL←HL+1
BC←BC-1
Repeat until
BC=0
x0x00 2 6/5μs
LDD(DE)←(HL)
DE←DE-1
HL←HL-1
BC←BC-1
x0x0 2 5μs
LDDR(DE)←(HL)
DE←DE-1
HL←HL-1
BC←BC-1
Repeat until
BC=0
x0x00 2 6/5μs
P/V is 0 if the result of BC-1 is 0, otherwise P/V=1

Search

Mnemonic       Symbolic Operation SZ5H4PNC sizetime
CPIA-(HL)
HL←HL+1
BC←BC-1
xx1 2 4μs
CPIRA-(HL)
HL←HL+1
BC←BC-1
Repeat until
A=(HL) or
BC=0
xx1 2 5/4μs
CPDA-(HL)
HL←HL-1
BC←BC-1
xx1 2 4μs
CPDRA-(HL)
HL←HL-1
BC←BC-1
Repeat until
A=(HL) or
BC=0
xx1 2 5/4μs

P/V is 0 if the result of BC-1 is 0, otherwise P/V=1
Z is 1 if A=(HL), otherwise Z=0

Absolute and relative JumP

Mnemonic       Symbolic Operation SZ5H4PNC sizetime
JP nnPC←nn xx 2 5μs
JP NZ,nnif Z=0 then PC←nn
otherwise continue
xx 2 3μs
JP Z,nnif Z=1 then PC←nn
otherwise continue
xx 2 3μs
JP NC,nnif C=0 then PC←nn
otherwise continue
xx 2 3μs
JP C,nnif C=1 then PC←nn
otherwise continue
xx 2 3μs
JP PO,nnif P=0 then PC←nn
otherwise continue
xx 2 3μs
JP PE,nnif P=1 then PC←nn
otherwise continue
xx 2 3μs
JP P,nnif S=0 then PC←nn
otherwise continue
xx 2 3μs
JP M,nnif S=1 then PC←nn
otherwise continue
xx 2 3μs
JP (HL)PC←HL xx 1 1μs
JP (IX)PC←IX xx 2 2μs
JP (IY)PC←IY xx 2 2μs
JR ePC←PC+e xx 2 3μs
JR C,eif(C==1):PC←PC+e
else continue
xx 2 3μs
2μs
JR NC,eif(C==0):PC←PC+e
else continue
xx 2 3μs
2μs
JR Z,eif(Z==1):PC←PC+e
else continue
xx 2 3μs
2μs
JR NZ,eif(Z==0):PC←PC+e
else continue
xx 2 3μs
2μs
DJNZ eB←B-1
if(B>0):PC←PC+e
else continue
xx 2
4μs
3μs

CALL and RETurn

Mnemonic       Symbolic Operation SZ5H4PNC sizetime
CALL nnSP←SP-2
(SP)←PCl
(SP+1)←PCh
PC←nn
xx 3 5μs
CALL NZ,nnif(Z==0):CALL nn
otherwise continue
xx 3 5μs
3μs
CALL Z,nnif(Z==1):CALL nn
otherwise continue
xx 3 5μs
3μs
CALL NC,nnif(C==0):CALL nn
otherwise continue
xx 3 5μs
3μs
CALL C,nnif(C==1):CALL nn
otherwise continue
xx 3 5μs
3μs
CALL PO,nnif(P==0):CALL nn
otherwise continue
xx 3 5μs
3μs
CALL PE,nnif(P==1):CALL nn
otherwise continue
xx 3 5μs
3μs
CALL P,nnif(S==0):CALL nn
otherwise continue
xx 3 5μs
3μs
CALL M,nnif(S==1):CALL nn
otherwise continue
xx 3 5μs
3μs
RETPCl←(SP)
PCh←(SP+1)
SP←SP+2
xx 1 3μs
RET NZif(Z==0):RET
otherwise continue
xx 1 3μs
1μs
RET Zif(Z==1):RET
otherwise continue
xx 1 3μs
1μs
RET NCif(C==0):RET
otherwise continue
xx 1 3μs
1μs
RET Cif(C==1):RET
otherwise continue
xx 1 3μs
1μs
RET POif(P==0):RET
otherwise continue
xx 1 3μs
1μs
RET PEif(P==1):RET
otherwise continue
xx 1 3μs
1μs
RET Pif(S==0):RET
otherwise continue
xx 1 3μs
1μs
RET Mif(S==1):RET
otherwise continue
xx 1 3μs
1μs
RETIPCl←(SP)
PCh←(SP+1)
SP←SP+2
xx 2 4μs
RETNPCl←(SP)
PCh←(SP+1)
SP←SP+2
IFF1←IFF2
xx 2 4μs
RST pSP←SP-2
(SP)←PCl
(SP+1)←PCh
PC←8*p
xx 1 3μs

Input/Output

Mnemonic       Symbolic Operation SZ5H4PNC sizetime

Bit set, reset and test

Mnemonic       Symbolic Operation SZ5H4PNC sizetime

Rotate and Shift

Mnemonic       Symbolic Operation SZ5H4PNC sizetime

Bits/Rotate and load

Mnemonic       Symbolic Operation SZ5H4PNC sizetime
LD A,RL(IX+d) xx 0 0μs

Interruptions

MEMPTR internal register

The MEMPTR is an internal 16 bits register of the Z80 CPU which is mostly used by the CPU to perform 16 bits operations (on values or addresses). The interresting part is that two bits (11 and 13) of this register seems to be copied in the bit 3 and 5 of the flag register. Some crazy russians recently cracked the MEMPTR algorithm to understand how each CPU instruction affect the MEMPTR.

Here is the original document which I used in the instructions sets above.

Download

Datasheets

Books and papers

documentations/devices/z80.txt · Last modified: 2009/04/15 18:11 by grim