Source: Wikipedia.

The programming model and register set are conventional and similar to many other processors, such as the related x86 family. The 8080 compatible registers AF, BC, DE, HL are duplicated as two separate banks in the Z80, where the processor can quickly switch from one bank to the other; a feature useful for speeding up responses to single level, high priority interrupts. The dual-register set makes sense as the Z80 (like most microprocessors at the time) was really intended for embedded use, not for personal computers, or the yet-to-be invented home computers. It also turned out to be quite useful for hard-optimized manual assembly coding.

The 8080 compatible registers:

• AF - 8-bit accumulator (A) and flag bits (F) carry, zero, minus, parity/overflow, half-carry (used for BCD), and an Add/Subtract flag (usually called N) also for BCD
• BC - 16-bit data/address register or two 8-bit registers
• DE - 16-bit data/address register or two 8-bit registers
• HL - 16-bit accumulator/address register or two 8-bit registers
• SP - stack pointer, 16 bits
• PC - program counter, 16 bits

Registers introduced with the Z80:

• IX - 16-bit index or base register for 8-bit immediate offsets
• IY - 16-bit index or base register for 8-bit immediate offsets
• I - interrupt vector base register, 8 bits
• R - DRAM refresh counter, 8 bits (msb does not count)
• AF' - alternate (or shadow) accumulator and flags (toggled in and out with EX AF,AF' )
• BC', DE', and HL' - alternate (or shadow) registers (toggled in and out with EXX)
• Four bits of interrupt status and interrupt mode status

There is no direct access to the alternate registers, instead two special instructions, EX AF,AF' and EXX, each toggles one of two multiplexer flipflops; this enables fast context switches for interrupt service routines: EX AF, AF' may be used alone (for really simple and fast interrupt routines) or together with EXX to swap the whole AF, BC, DE, HL set; still much faster than pushing the same registers on the stack (slower, lower priority, or multi level interrupts normally use the stack to store registers).

The refresh register, R, increments each time the CPU fetches an opcode (or opcode prefix) and has therefore no simple relationship with program execution. This has sometimes been used to generate pseudorandom numbers in games, and also in software protection schemes.

The interrupt vector register, I, is used for the Z80 specific mode 2 interrupts (selected by the im 2 instruction). It supplies the base address for a 128-entry table of service routine addresses which are selected via a pointer sent to the CPU during an interrupt acknowledge cycle. The pointer identifies a particular peripheral chip and/or peripheral function or event, where the chips are normally connected in a so called daisy-chain for priority resolution. Like the refresh register, this register has also sometimes been used creatively.

The tables below list all the Z80 instructions (including the 'undocumented').
On the Amstrad CPC/Plus, the Z80 is clocked to 4MHz. The instructions timing is given in microseconds since all the instructions are rounded up to the nearest M-Cycle (because of the hardware design and bus sharing with the video devices).

Notes:

• d is a 8bit signed number (-128 to 127)
• n is a 8bit number
• nn is a 16bits number
• r and s means any of the registers A,B,C,D,E,H,L
• rr and ss means any of the double registers BC,DE,HL,SP
• qq means any of the double registers BC,DE,HL,AF

• x/y time is shown for repeating or conditionnal instructions. x is the time when the instruction repeat itself or if it's condition is true. y otherwise.

Flags notations:

• • flag is not affected
• x flag is unknown
• 0 flag is reset
• 1 flag is set
• ★ flag is affected according to the result of the operation

The MEMPTR is an internal 16 bits register of the Z80 CPU which is mostly used by the CPU to perform 16 bits operations (on values or addresses). The interresting part is that two bits (11 and 13) of this register seems to be copied in the bit 3 and 5 of the flag register. Some crazy russians recently cracked the MEMPTR algorithm to understand how each CPU instruction affect the MEMPTR.

Here is the original document which I used in the instructions sets above.

• MEMPTR, esoteric register of the ZiLOG Z80 CPU by Boo-boo (first and draft English translation by Vladimir Kladov).

• Z80 CPU User Manual (2005)(Zilog)
• Z80 Product Specification (1989)(Zilog)
• Z80 Program Interrupt Structure (1978)(Zilog)
• The Undocumented Z80 Documented (2005)(Sean Young)

• Z80 Assembly Language Programming Manual (1977)(Zilog)
• Z80 Assembly Language Subroutines (1983)(Lance A Leventhal)(Osborne)
• Programming the Z80 3rd Edition (1980)(Rodnay Zaks)(Sybex)